1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device for storing and retaining information by utilizing different polarization states of a ferroelectric film which is interposed between opposite electrodes of a capacitor.
2. Description of the Related Art
In general, a semiconductor memory device incorporating a ferroelectric material (hereinafter referred to as a "ferroelectric memory device") is a non-volatile memory which performs data storage based on the polarization directions of the ferroelectric material. FIG. 6 chiefly shows a memory cell portion of a conventional non-volatile semiconductor memory device incorporating a ferroelectric film (see, for example, T. Sumi et al., 1994 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 268-269).
The ferroelectric memory device shown in FIG. 6 mainly includes a plurality of memory cells MC arranged in a matrix of rows and columns, where each memory cell includes a capacitor Cs consisting essentially of a ferroelectric film interposed between opposite electrodes, and a MOS transistor Qc whose source or drain is coupled to one of the electrodes of the capacitor Cs (hereinafter, the other electrode of each capacitor Cs will be referred to as a "plate electrode", as described below).
The ferroelectric memory device further includes a plurality of word lines WL0 to WL2m+1 provided for the respective rows of memory cells MC so as to be coupled to the gates of the transistors Qc of the respective rows of memory cells MC. When at a "selected" level, the word lines WL0 to WL2m+1 place these memory cells MC in a "selected" state.
The ferroelectric memory device further includes a plurality of bit lines BL0 to BLn and a plurality of bit lines /BL0 to /BLn provided for the respective columns of memory cells MC so as to be coupled to the drains of the transistors Qc of the respective columns of memory cells MC.
The ferroelectric memory device further includes a plurality of plate lines PL0 to PLm such that one plate line is provided for every two rows of memory cells MC and coupled to the "plate electrodes" of every two corresponding capacitors Cs.
The ferroelectric memory device further includes a plurality of MOS transistors T0 to T2m+1 provided for the respective word lines WL0 to WL2m+1 such that their gates are coupled to the respective word lines, their sources are coupled to the respective plate lines, and their drains are coupled to a common drive line DL.
Finally, the ferroelectric memory device includes a plate driving signal generation circuit 1 for supplying a plate driving signal to the drive line DL.
In the present specification, a memory cell which stores information by utilizing the action of a ferroelectric film will be referred to as a "ferroelectric memory cell".
A read operation of the above-described ferroelectric memory device will be described with reference to the timing chart shown in FIG. 7.
In a stand-by state before the word line (e.g., WL0) rises to a "selected" level (i.e., a HIGH level), the bit lines BL0 to BLn, bit lines /BL0 to /BLn, and drive line DL are at a ground potential. As the word line WL0 rises to a HIGH level, the memory cells MC coupled to the word line WL0 become selected; at the same time, the transistor T0 becomes conductive so that the plate line PL0 is coupled to the drive line DL. Then, the plate driving signal shifts to a plate driving voltage Vp1, so that the plate driving voltage Vp1 is supplied to the plate line PL0. As a result, the information stored in the memory cells MC can be read onto the bit lines BL0 to BLn. A reference cell (not shown) is selectively coupled to the bit lines /BL0 to /BLn (which are complementary to the bit lines BL0 to BLn) so as to place the bit lines /BL0 to /BLn at a reference voltage level. The reference voltage level is prescribed (as conveniently accomplished by the adjustment of the capacitor size of the reference cell) to be an intermediate potential between the respective bit line potentials corresponding to "1" and "0" to be stored in a given memory cell MC. The information which is stored in each selected memory cell can be read so as to become available to the outside, by amplifying a differential voltage between corresponding ones of the bit lines BL0 to BLn and complementary bit lines /BL0 to /BLn. Thereafter, the plate driving signal shifts to the ground potential so as to place the plate line PL0 at the ground potential, as a result of which the information which was previously stored in the selected memory cells is rewritten thereto.
In accordance with the conventional ferroelectric memory device shown in FIG. 6, any information is stored by inducing either a positive or negative polarization of the ferroelectric film of the capacitor Cs of each memory cell MC, and any information thus stored is read by detecting the state of the induced polarization. However, since this requires supplying a predetermined potential Vp1 to the plate line as described above, not only the memory cell whose stored information is read but also the other memory cells in the same row or column will be driven. Also, the ferroelectric material incorporated in the capacitor Cs boosts the capacitance up to a value which is larger than that typically used in a usual DRAM.
Moreover, the plate lines are typically formed of precious metals, e.g., Au, Pt, and Ru for matching with the ferroelectric material. It is difficult to form a relatively thick film out of such precious metals due to their processibility problems, and it is undesirable to employ broad wiring leads in terms of miniaturization of the device and enhancement in the mounting density of the device. Hence, the plate lines will inevitably be designed so as to have a relatively high resistance value, which results in a large time constant. This in turn results in a relatively long time being required for driving the plate lines, thereby hindering high-speed operations of the device. In addition, charging and discharging plate lines disadvantageously increases the power consumption of the device.
In summary, the following problems may arise in the above-described conventional ferroelectric memory device in which the plate lines must be driven to a predetermined potential every time access is made: a relatively long time being required for driving the plate lines, difficulties in achieving high-speed operations, and increased power consumption due to the charging and discharging of plate lines.